tincr::designs Namespace Reference

The designs ensemble encapsulates the design class from Vivado's Tcl data structure. More...

Functions
	test args
	test_proc proc args
	new name ?part?
	get args
	summary
	clear
	diff design1 ?design2? ?filename?
	get_route_throughs
	edif filename
	get_buses
	get_design_buses
	remove_route_throughs route_throughs

Detailed Description

The designs ensemble encapsulates the design class from Vivado's Tcl data structure.

Function Documentation

clear()

tincr::designs::clear

Delete all of the cells, nets, and ports in a design. This is faster than calling close_project and reopening a design.

diff()

tincr::designs::diff			design1 ?design2? ?filename?

Reports the differences between two designs. This includes differences in the netlist, placement, and routing, as well as their relevant attributes.

Parameters

design1	The first design to compare.
design2	The second design to compare. If this parameter is omitted or empty, the current design will be used.
filename	The file that the results will be written to. If this parameter is omitted or empty, stdout will be used.

edif()

tincr::designs::edif			filename

Write this design to an electronic design interchange format (EDIF) file.

Parameters

filename

The file that this design's EDIF representation will be written to.

get()

tincr::designs::get			args

Queries Vivado's object database for a list of design objects that fit the given criteria. At the moment, this is just a wrapper function for Vivado's get_designs command.

get_buses()

tincr::designs::get_buses

Get a list of all buses in the current design.

Returns

A list of all buses in the current design.

get_design_buses()

tincr::designs::get_design_buses

Get a dictionary containing information about all of the buses in the current design. The dict format is as follows:

buses
|
|->    <bus0>
|->    direction = IN/OUT/INOUT
|->    start = start wire
|->    stop = end wire
|->    width = bus width
+->    ports = { <port0>, <port1>, ... }
|->    <bus1>
:

Returns

A Tcl dict object containing bus information.

get_route_throughs()

tincr::designs::get_route_throughs

Get the route-throughs in a design. This includes both BEL- and site-level route-throughs.

Returns

A list of bel_pin objects, one for each route-through.

new()

tincr::designs::new			name ?part?

Create a new design.

Parameters

name	The name of the new design.
part	The FPGA part the new design will target.

Returns

The newly created design object.

remove_route_throughs()

tincr::designs::remove_route_throughs			route_throughs

Remove the route-throughs in a design. This function replaces all route-throughs with BUF cells.

summary()

tincr::designs::summary

Return a dictionary that contains a summary of the current design. tincr::designs diff uses this procedure to compare designs.

test()

tincr::designs::test			args

Executes all unit tests for every proc in the designs ensemble.

Parameters

args	The configuration arguments that will be passed to the tcltest unit testing suite.

test_proc()

tincr::designs::test_proc			proc args

Executes all unit tests for a particular proc in the designs ensemble.

Parameters

proc	The proc to run the unit tests for.
args	The configuration arguments that will be passed to the tcltest unit testing suite.