Basic Yosys to F4PGA

Setting up Yosys and F4PGA

Install F4PGA and follow all of the steps here.

  1. Using the command line type the following

>>> cd ~/opt/f4pga//xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/tcl

  1. Open xc7.f4pga.tcl

  • Right before the write_blif if-else part (at the very bottom), add “hierarchy -purge_lib”

  • Then, add option “-blackbox” to both write_blif commands

Download all of the following files

simpleCounter.sv

simpleCounter.xdc

new_constraints.txt

tmr_script.py

common.mk

Makefile

Running Yosys, SpyDrNet TMR, and F4PGA

Once all of the files have been downloaded type navigate to their location and type in the command line

>>> make -C .

or

>>> make download -C .

Note: This will run Yosys and F4PGA then download the bitstream to the board

Programming Device

To download the bitstream to the board using the command line

>>> make download

Verifying if the Design Works

The counter in this design increments when btnc is pressed. Once it reaches a count of 15 (4 LEDs are on) it rolls over to 0 and starts counting up again. If at any point btnu is pressed the count is reset to 0. Since this is a TMR design there should be 3 sets of 4 leds in total.

  • Set 1 (LEDS 0-3), Set 2 (LEDs 5-8), Set 3 (LEDs 10-13)

Note

  1. This example was designed using a BASYS 3 board. If a different FPGA is being used the simpleCounter.xdc and the new_constraints.txt file will need to be modified accordingly.

  2. Make sure all of the files are in the same location. If not the path to the file will need to be specified in the Makefile

  3. If getting errors with common.mk make sure that all of the indents are tabs and not spaces.