Built In FPGA Architectures

SpyDrNet has built in libraries for the following primitive libraries:

  • Xilinx 7-Series

  • F4PGA Xilinx 7-Series

  • Lattice LIFCL

An optional parameter can be parsed to parse() which will tell the parser to load in the specified primitive library during parsing. This allows primitive information to be known (particularly port directions) even if though it may not be defined in the netlist (as a cell define module or a blackbox).

The supported types are found under spydrnet.util.architecture

When a built in architecture parameter is passed, the parser uses the PrimitiveLibraryReader class to load in the primitive library and populate the netlist definitions with information. See below.

class spydrnet.parsers.primitive_library_reader.PrimitiveLibraryReader(architecture, netlist)[source]

A class to extract primitive port information from a Verilog file and insert it into the netlist. The input file is parsed using the Verilog Parser and if any module information is found for a definition in the given netlist, the port information (i.e. directions) is added.

Parameters:

  • architecture - the targeted architecture. Must be a type from spydrnet.util.architecture

  • netlist - the current netlist