.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "auto_examples/vivado/AND_to_OR.py"
.. LINE NUMBERS ARE GIVEN BELOW.

.. only:: html

    .. note::
        :class: sphx-glr-download-link-note

        :ref:`Go to the end <sphx_glr_download_auto_examples_vivado_AND_to_OR.py>`
        to download the full example code

.. rst-class:: sphx-glr-example-title

.. _sphx_glr_auto_examples_vivado_AND_to_OR.py:


============================
Modify Netlist with SpyDrNet
============================

This example shows how SpyDrNet can parse in a netlist, modify it, and compose a new netlist.

The script parses in a simple example netlist that is just an AND gate implemented with a LUT. The instance of the LUT2 primitive definition is found, and then the properties of it are modified to change the configuration of the LUT.

Below are tables of an AND gate and an OR gate. A LUT is configured by setting the ``'value':'<LUT_configuation>'`` pair in the metadata ``[EDIF.properties]`` dictionary associated with the LUT2 instance. The ``'<LUT_configuration>'`` string is composed from the output of an n-input truth table in hexadecimal. Below is a demonstration of how to determine the ``'<LUT_configuration>'`` string.

+-----------+
| AND gate  |
+---+---+---+
| A | B | Q |
+===+===+===+
| 0 | 0 | 0 |
+---+---+---+
| 0 | 1 | 0 |
+---+---+---+
| 1 | 0 | 0 |
+---+---+---+
| 1 | 1 | 1 |
+---+---+---+

The output Q for the AND gate is the following: ``Q = 4'b1000``, or in hexadecimal, ``Q=4'h8``. Replace '<LUT_configuration>' with ``'4'h8'``

+-----------+
| OR gate   |
+---+---+---+
| A | B | Q |
+===+===+===+
| 0 | 0 | 0 |
+---+---+---+
| 0 | 1 | 1 |
+---+---+---+
| 1 | 0 | 1 |
+---+---+---+
| 1 | 1 | 1 |
+---+---+---+

The output Q for the OR gate is the following: ``Q = 4'b1110``, or in hexadecimal, ``Q=4'hE``.

The netlist example that is loaded in has a LUT configured to be an AND gate, but with SpyDrNet, you can modify that LUT to be something else. The LUT configuration ``'4'h8'`` (an AND gate) for the LUT in the netlist will be changed to ``'4'hE'`` (an OR gate) in this example.

After making this configuration, the new netlist will be composed twice, showing that SpyDrNet can either create an EDIF netlist file or a Verilog netlist file that both represent the same netlist.

.. GENERATED FROM PYTHON SOURCE LINES 49-75

.. code-block:: default


    import spydrnet as sdn


    # Change this line to change the configuration of the LUT in the design.
    LUT_CONFIG = 0xE

    logic_gate_netlist = sdn.load_example_netlist_by_name("AND_gate")

    # Alternatively you can parse in your own netlist by changing the line below.
    # logic_gate_netlist = sdn.parse('<my_netlist.edf>')


    # Find the LUT2 definition
    for definition in logic_gate_netlist.get_definitions():
        if definition.name == "LUT2":
            lut_instances = definition.references
            # Once the LUT2 definition has been found, go through its instances
            for instance in lut_instances:
                properties = instance["EDIF.properties"]
                # Change the value in the properties of the LUT2 instance
                properties[0]["value"] = "4'h" + str(hex(LUT_CONFIG)).upper()[2:]

    # The netlist is composed into both an EDIF file and also in a Verliog file
    sdn.compose(logic_gate_netlist, "OR_gate.edf")
    sdn.compose(logic_gate_netlist, "OR_gate.v")


.. rst-class:: sphx-glr-timing

   **Total running time of the script:** (0 minutes 0.000 seconds)


.. _sphx_glr_download_auto_examples_vivado_AND_to_OR.py:

.. only:: html

  .. container:: sphx-glr-footer sphx-glr-footer-example




    .. container:: sphx-glr-download sphx-glr-download-python

      :download:`Download Python source code: AND_to_OR.py <AND_to_OR.py>`

    .. container:: sphx-glr-download sphx-glr-download-jupyter

      :download:`Download Jupyter notebook: AND_to_OR.ipynb <AND_to_OR.ipynb>`


.. only:: html

 .. rst-class:: sphx-glr-signature

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