Bootcamp is a summer program for new students (mostly undergraduates) which provides them training and experience computing technologies required to perform research in a variety of Computer Engineering topics.

IIRM-URA is a research collaboration, funded by the Defense Thread Reduction Agency (DTRA), that brings together several different universities and research labs to investigate the effect radiation has on materials and devices. The BYU team is focused on investigating and modeling the effect radiation has on SoCs (Systems On a Chip). Currently, efforts are centered around Xilinx MPSoC chip and how it fails under radiation.

This work focuses on developing techniques to ensure that FPGA designs remain secure throughout the hardware compilation process. Equivalence checking tools are used to determine whether initial RTL circuit or IP modules are equivalent to the placed and routed FPGA bitstream.

Shorty is a project that explores different applications of placing configurable short circuits on Xilinx FPGAs. Applications include localized accelerated aging, hardware trojans, watermarking, and more.

Our research lab actively contributes to several different open-source FPGA tools and compilers, particularly those in the Symbiflow ecosystem.

This project focuses on developing tools to analyze and understand the netlists from unknown FPGA bitstreams. This includes rebuilding design hierarchy, identifying multi-bit words, and locating known IP cores.

COAST is a set of compiler tools that provides automated software protection from single-event effects. Users can select portions of their porgram to protect, and the compiler will automatically duplicate or triplicate instructions. COAST currently supports ARM, RISC-V and MSP430 processor architectures, and has been validated by several tests using the LANSCE neutron beam.

PYNQ PRIO is an addition to the Xilinx PYNQ project. With the integration of PRIO the PYNQ package is augmented with two powerful new features. First is the addition of partial reconfiguration, allowing users to reconfigure targeted sections of the FPGA fabric at will. Second is device tree overlay support allowing users to dynamically load, unload and reload hardware specific Linux Kernel drivers, making the Kernel as reconfigurable as the hardware it supports. Currently PRIO is fully integrated with the Xilinx PYNQ project.

This project demonstrates the use of partial reconfiguration to dynamically configure a custom video processing pipeline during run-time.