News

Professor traveled to Turino, Italy, to present the culminating PhD work of Hayden Cook, at the International Conference on Field-Programmable Logic and Applications (FPL). The work, titled “Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA”, explores how one can intentionally age different pieces of an FPGA, including individual LUTs and routing segments.

Nathan Baker (masters student), Weston Smith (undergraduate student), and Professor Wirthlin traveled to Ottawa, Canada, for the 2024 IEEE Nuclear & Space Radiation Effects Conference (NSREC). Nathan presented his work “Post-Radiation Fault Injection for a Complex FPGA Designs,” and Weston presented his work, “A Parallelized Neutron Radiation Testing Technique to Understand Failures Within a Complex SoC.”

Professor Jeff Goeders traveled to Orlando, Florida, to attend the 2024 International Symposium On Field-Programmable Custom Computing Machines (FCCM). He presented Daniel Hutchings’ Master’s work, “Toward FPGA Intellectual Property (IP) Encryption from Netlist to Bitstream”. This work was published in the ACM TRETS journal, and describes a novel method to encrypt FPGA IP through the CAD flow and into the bitstream.

Undergraduate researcher Dallin Wood, traveled along with Professors Wirthin and Goeders, to the Little Mountain Test Facility in Ogden, Utah to use the LINAC for computer reliability testing. The research project studied how a simply microcontroller (attiny85) would respond to radiation.

Professor Goeders attend the 2024 Hardware Reverse Engineering Workshop (HARRIS 2024), hosted by Ruhr University in Bochum, Germany. He gave a talk titled, “Leveraging FPGA Reverse Engineering for Secure CAD Flows,” that discussed how recent tools in the FPGA open-source community can be leveraged for good, improving the security of FPGA CAD flows.

Professor Wirthlin and Goeders travel with six students to report on 2023 activities and propose projects for 2024 for the NSF SHREC center.

Reilly McKendrick (PhD student) and Professor Jeff Goeders traveled to Yokohama, Japan to attend the International Conference on Field-Programmable Technology. Reilly presented the paper “Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison”, co-authored by himself, Professor Goeders, and Keenan Faulkner.

Professor Jeff Goeders traveled to Toulouse, France to present at the 2023 RADECS conference. The poster was titled, “The Effects of Gamma Ray Dose on Dynamic Operation of a Commercial FRAM Device”, co-authored by BYU students Wesley Stirk and Nathan Harris, and Professor Mike Wirthlin.

Hayden Cook traveled to Gothenburg, Sweden to attend the 2023 International Conference on Field-Programmable Logic and Applications (FPL). While there, Hayden presented a poster on his short paper, “Improving the Reliability of FPGA CRO PUFs”, co-authored by BYU student Zephraim Tripp and Professor Brad Hutchings and Jeffrey Goeders.

During the week of August 28-September 1st, Michael Bjerregaard and Garrett Smith had the opportunity to participate in a radiation test at the Lawrence Berkeley National Laboratory (LBNL). They attended to support a test of the Versal DUT card created by the Xilinx Radiation Test Consortium and to validate the function of the BYU JTAG configuration module (JCM). They were able to help finish setting up to power cabling for the Versal DUT card and place it in the beam. The system performed successfully and we were able to scrub configuration upsets in the Versal part while logging both the upsets and the statuses reported from the part itself. Although there were a number of setbacks, during the setup and test run, the experiment successfully collected programmable logic CRAM upsets at a high rate and determined cross section measurements. The BYU team is looking forward to testing again with more complex designs and more stringent testing conditions.

Professor Jeff Goeders organized the 2023 DAC System Design Contest, where teams competed to perform fast and accurate image recognition on an embedded FPGA or GPU platform. The contest was sponsored by AMD, and held in conjunction with the 2023 Design Automation Conference (DAC), which was held in San Francisco, California. Professor Goeders held a special session at DAC where the winning teams presented their design solutions.

Undergraudate Weston Smith, along with Professor Mike Wirthlin, traveled to the ChipIr Beamline at the ISIS Neutron and Muon source at the Rutherford Appleton Laboratory, UK, to verify the reliability of various computer reliability methodologies. The experiments performed at ChipIr were testing methodologies for multicore SoC (System-on-a-Chip), various DRAM devices, a TMR RISCV processsor and Linux on a MPSOC. The image on the left are the experiments in the testing environment and the image on the right is Weston Smith setting up the experiment.

PhD students Andrew Wilson and Hayden Cook, along with Professor Jeff Goeders, attended the 2023 International Symposium on Field-Programmable Gate Arrays (FPGA) and Workshop on Security for Custom Computing Machines (SCCM). Andrew presented his paper, “Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC”, co-authored by BYU students Nate Baker, Ethan Campbell, and Jackson Sahleen and Professor Mike Wirthlin. Professor Goeders co-organized the SCCM workshop, where Hayden gave a presentation titled “Cloning the Unclonable: Physically Cloning an FPGA RO PUF”.

Researchers from the CCL traveled to the Los Alamos Neutron Science Center (LANSCE) to verify the reliability of various computer reliability methodologies. The experiments performed at LANSCE were a testing methodologies for multicore SoC (System-on-a-Chip), an improved Linux PCAP scrubber, radiation hardened softcore processors, a DDR memory module and attempting to generate bit upsets data for FRAM chips continually performing reads and writes. The image on the left are the experiments exposed to the neutron radiation beam and on the right are researchers involved.

PhD student Hayden Cook, along with Professor Jeff Goeders, virtually attended the 2022 IEEE International Conference on Field-Programmable Technology (FPT) (FPT). Hayden presented his paper, “Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF”, co-authored by BYU students Jonathan Thompson and Zephram Tripp and professor Jeffrey Goeders as well as retired professor Brad Hutchings. This paper ended up winning FPT’s best paper award.

Researchers from the CCL and Sandia National Laboratory traveled to the Little Mountain Test Facility in Ogden, Utah to use the LINAC for computer reliability testing. An SRAM chip (a commonly used component in bigger devices) was irradiated at varying intensities and durations to characterize its response. The people in the image on the left are (from left to right) Dolores Black (SNL), Jeff Black (SNL), Wesley Stirk (CCL), Roy Cuoco (SNL), Mike Wirthlin (CCL), and Jeff Goeders (CCL).

Andrew Keller successfully defended his PhD dissertation, “Partial Circuit Replication for Masking and Detecting Soft Errors in SRAM-Based FPGAs”. Andrew is now starting a full-time job at L3Harris in Salt Lake City.

Students, faculty, and their spouses, got together for a party to celebrate the end of a successful summer of research. Lots of fun was had chatting and getting to know each other with plenty of cheeseburgers, snacks and ice cream.

Students from the CCL traveled to the Los Alamos Neutron Science Center (LANSCE) to perform a variety of experiments related to computer reliability. Experiments included testing of a Linux-based PCAP scrubber, radiation hardened softcore processors, SoC (System-on-a-Chip) radiation testing methodologies, and FPGA fabric characterization under radiation. The image on the left shows the experiment boards lined up for the neutron radiation beam. The image on the right shows the participating students on the first day of the experiments (and the first day of school).

Hayden Cook (Master’s student) gave a remote presentation at the 30th International Conference on Field-Programmable Logic and Applications on “Using Novel Configuration Techniques for Accelerated FPGA Aging”.